CODD synchronisation system proposal

Numerical integration

A fast ADC digitises the analogue PU signal at a rate of h=512. If the gate and BLR are off, nothing more happens. If the BLR is on, the samples are applied to a numerical low-pass filter, to calculate the base-line level. If the gate is on, the difference of the samples and the current base line are accumulated into a numerical integrator. At the end of the gate period, the final result is stored into the memory, and the integrator is cleared. (See figure.)